The present invention relates to an improved method of semiconductor testing, burning-in, and packaging.
Both standard module burn-in and wafer burn-in schemes are wasteful of time space and resource. Module burn-in requires dicing, bond, assembly, and test before burn-in, adding considerable expense to modules that fail burn-in. Wafer burn-in permits burn-in before dicing, saving the packaging cost for failing chips, but it obviously requires the inclusion of the failing chips on the wafer in the burn-in apparatus. Provision must then be provided for disconnecting shorted chips or handling very high currents while providing voltage uniformity. Thus, wafer burn-in is most cost effective for high yielding wafers.
Chip or die burn-in schemes like IBM's R3 process and TI's Diemate process avoid the packaging steps required by module burn-in. Only tested bare chips are burned-in. The R3 process permits simultaneous burn-in of a large array of chips. The chips are solder bump mounted on a ceramic substrate which can be reused a number of times. This provides advantage over the Diemate process which burns in only one chip at a time in each fixture. But the cost of the R3 process can still be expensive since the substrate can only be reused about ten or twenty times. And there is substantial cost for aligning and attaching chips to the substrate and then for removing them and preparing them for reattaching to a final substrate once burn-in is complete. Therefore the cost of producing known good die with module burn-in, wafer burn-in, the R3 process, or the Diemate process can be quite high. Thus, a better solution for test and burn-in is needed that lowers the cost, and that solution is provided by this invention.